The present invention relates to a method of manufacturing a printed circuit board capable of adjustment of the aspect ratio of via holes and to a printed circuit board manufactured by the manufacturing method.
In recent years, the pitch between terminals of semiconductor chips such as BGA (ball grid array) packages has been reduced. There is a need to reduce the pitch between lines/lands provided on printed circuit boards for mounting of semiconductor chips as well as to reduce the diameter of via/through holes.
A land is a round or polygonal element of a circuit pattern provided on an insulating substrate for a printed circuit board. Terminals of a semiconductor chip are connected to lands, and via holes or through holes are formed in lands. Lines are portions of a circuit pattern other than lands.
When lines are formed with a reduced pitch, it is desirable to reduce the thickness of the metal conductor layer. This is because if the thickness of the metal conductor layer is thick when thin lines having a reduced line spacing (hereinafter referred to as fine lines) are formed by etching, etching cannot be suitably performed so as to avoid occurrence of metal residues (including an anchor) and failure to insulate lines from each other.
In a printed circuit board, openings for via holes or through holes are formed in an insulating substrate and plating is performed on the openings to form via holes or through holes. However, when plating is performed on the openings for via holes or through holes, it is performed on the entire insulating substrate. If plating is performed on the metal conductor layer in an area where lines will be formed, the entire metal layer becomes thick and it is difficult to reliably perform etching so that the lines have a predetermined line and a line spacing. This is a disadvantage to forming of fine lines.
On the other hand, as printed circuit boards become finer, the via hole diameter is reduced. In order to reduce the aspect ratio of via holes, it is necessary to reduce the thickness of the insulating layer (or dielectric layer). The aspect ratio is defined as the quotient of division of the depth of a via hole by the diameter of the via hole. If the insulating layer is a prepreg containing glass cloth, the thickness of the insulating layer is limited by the thickness of the glass cloth and cannot be reduced. In a case where via holes are filled with a plating, it is advantageous to reduce the diameter of the via holes from the viewpoint of the manufacturing time and the plating filling effect. If the diameter of the via holes is reduced, the aspect ratio of the via holes becomes higher and the plating liquid cannot flow smoothly to the bottom of each via hole. As a result, the plating layer at the bottoms of the via holes is made nonuniform in thickness and there is a possibility of occurrence of a crack in the plating layer at the reflow temperature at the time of mounting or in a thermal cycle test and, hence, a possibility of failure to establish interlayer connection.
In order to establish interlayer connection with reliability, it is necessary to increase the plating layer of in the via holes. However, the metal conductor layer in an area where lines are to be formed is also plated simultaneously with plating on the via holes to make the entire metal layer thick, as described above.
This is a disadvantage to forming of fine lines. As described above, it is difficult to reliably perform plating on via holes and to form fine lines.
The thickness of the plating layer formed by plating processing in the process of manufacturing a printed circuit board varies largely. Lines formed on the printed circuit board vary largely in thickness since the plating layer is superposed on metal foil. Also, at the time of etching for forming the lines, failure to completely performing etching may occur due to variation in thickness of the plating layer and there is a possibility of short circuit between the lines in some place.
In some cases, fine lines are formed in such a manner that metal foil on the insulating substrate is separated and plating is then performed to form the lines. However, there is a possibility of the bond strength of the plating layer to the insulating substrate becoming lower than that of the metal foil, i.e., failure to obtain the desired metal bond strength. There is a risk of the plating layer being separated from the insulating substrate when the completed printed circuit board is subject to various tests including a thermal shock test. If the plating layer is separated, the printed circuit board cannot be used as the product. In a case where plating processing is performed directly on an insulating member, there is a possibility of a catalyst such as palladium used in plating processing remaining as a residue to cause insulation degradation. If the catalyst remains as a residue between conductors, there is a risk of occurrence of failure phenomenon such as short circuit between pads when gold plating processing is performed and insulation degradation caused by an electrocorrosion test.
Japanese Patent Laid-Open Publication No. 50-41056 and Japanese Patent Laid-Open Publication No. 01-129494 disclose methods of manufacturing a printed circuit board by performing plating two times on through holes. It is possible to prevent occurrence of a crack in the plating layer by performing plating two times on through holes. Interlayer connections via the through holes can be established with reliability. However, plating is effected on metal foil as well as on through holes. Therefore, it is difficult to form fine lines even if interlayer connection can be established with reliability.
Japanese Patent Laid-Open Publication No. 03-175695 discloses a method of manufacturing a printed circuit board by performing plating on through holes after forming a circuit pattern. Plating is performed two times to ensure interlayer connection between the through holes. However, formed lines are also plated, so that it is difficult to form fine lines. Further, according to a drawing in Publication No. 03-175695, a plating layer is also formed on a side wall of the circuit pattern. Lines are made thicker by the thickness corresponding to the plating layer. The difficulty in forming fine lines is further increased thereby.
Japanese Patent Laid-Open Publication No. 04-62892 discloses a method of plating on through holes. This patent publication relates to a challenge to improve the reliability of connection via a through hole. The challenge is accomplished as described below. A circuit pattern is formed on an insulating substrate, and a mask is provided on the circuit pattern. An opening is formed in the insulating substrate by an operation from above the mask, and the mask on the periphery of the opening is also removed. Plating is performed on an inner opening surface to complete a through hole. According to FIG. 1 of Publication No. 04-62892, a portion on the periphery of the through hole is stepped. That is, the land at the through hole is stepped. The reliability of connection via the through hole in a thermal cycle test can be improved by stepping the land at the through hole. Publication No. 04-62892, however, includes no description of formation of fine lines and adjustment of the aspect ratio to a low value and differs from the present invention in terms of object.